Impact of Electrical Stress on Defect Generation in Thin GeO2/Ge Gate Stacks Fabricated by Thermal Oxidation

The impact of electrical stress on the defect generation behaviors in thin GeO
₂
/n-Ge gate stacks has been investigated through the measurement of the time-dependent dielectric breakdown (TDDB) and the stress-induced leakage current (SILC) characteristics. A multiple-spot breakdown (BD) event is confirmed, as well as a larger SILC generation probability compared with that in SiO
₂
/Si structures. It is found that the slow trap generation is dominant by the amount of injected electron fluence (Qinj), and the fix charge generation is attributed to bothQinj and GeO
₂
thickness.