Cartridge thermal design of Pentium/sup (R)/ III processor for workstation: giga hertz technology envelope extension challenges

This paper highlights thermal challenges of the Pentium/sup (R)/ III Xeon/sup TM/ processor and materials, and thermal management methods. Cartridge technology development to address thermal issues in a systematic manner and certify new cartridge technology for the 733 MHz lead product and for technology extension up to 1 GHz are discussed. This paper is in three sections. The first describes thermal impedance theory, junction to plate thermal impedance (R/sub jp/) metrology and thermal requirements/targets of cartridge processor thermal design. Thermal modeling using FEA was used to study changes in the nonuniform power junction to plate thermal relation resistance in response to the uniform power R/sub jp/, as well as core and on-die integrated cache power level variations. Thermal test vehicle design to support DOE activities is also illustrated. The second section describes material characterization and validations carried out using this thermal metrology to develop thermal interface materials (TIM) for cartridge packaging. Material development and certification activities of a phase change TIM for 733 MHz processor thermal requirements are described. In the last section, thermal optimization studies driven by technology extensions (800 MHz, 1 GHz) are discussed. For the 800 MHz extension, TIM optimization to improve existing phase change TIM thermal performance was performed. This was achieved by reducing TIM bond line thickness (BLT) via mechanical design and cartridge system electrical test optimizations. Statistical optimization approaches and their implications for cartridge thermal design under use conditions are also discussed.