Flip chip pin grid array (FC-PGA) packaging technology

As microelectronics moves toward greater levels of integration, functionality and performance, packaging technology complexity grows in direct proportion. With Si process evolution to finer feature sizes, microprocessor designs are achieving higher system clock speeds. As a result, the level of integration and interconnect density between processor chips and substrate has increased tremendously. This brings an array of challenges for package design, substrate technology and assembly process development. For highly integrated packaging at competitive cost, the flip chip pin grid array package (FC-PGA) is proposed as an innovative socketable solution which includes use of laser drilled blind/buried vias on PTH and SMT pins to ease routing and alleviate loop inductance. Use of an existing PGA socket infrastructure expedites OEM acceptance of the new package design in various configurations. This paper describes key features of FC-PGA and technical challenges encountered in FC-PGA design/validation and packaging process development, such as solder composition selection, SMT pin technology optimization, and resolution of via delamination and flip chip solder bump nonwetting problems. FC-PGA package design and process development efforts have demonstrated the feasibility of high density flip chip interconnect on organic substrates and high speed bus functionality with low cost, high yield, manufacturable and reliable packaging solutions, which have been utilized in Pentium/sup TM/ III microprocessors.