BSIM4 gate leakage model including source-drain partition

Gate dielectric leakage current becomes a serious concern as sub-20 /spl Aring/ gate oxide prevails in advanced CMOS processes. Oxide this thin can conduct significant leakage current by various direct-tunneling mechanisms and degrade circuit performance. While the gate leakage current of MOS capacitors has been much studied, little has been reported on compact MOSFET modeling with gate leakage. In this work, an analytical intrinsic gate leakage model for MOSFET with physical source/drain current partition is developed. This model has been implemented in BSIM4.