A networked FPGA-based hardware implementation of a neural network application

Describes a networked FPGA-based implementation of the FAST (Flexible Adaptable-Size Topology) architecture, an artificial neural network (ANN) that dynamically adapts its size. Most ANN models base their ability to adapt to problems on changing the strength of the interconnections between computational elements according to a given learning algorithm. However, constrained interconnection structures may limit such ability. Field programmable hardware devices are very well adapted for the implementation of ANNs with in-circuit structure adaptation. To realize this implementation, we used a network of Labomat-3 boards (a reconfigurable platform developed in our laboratory), which communicate with each other using TCP/IP or a faster direct hardware connection.