Logic synthesis for CPLDs and FPGAs with PLA-style logic blocks

PLA-style logic blocks can be used as the storage elements found in FPGAs and CPLDs. PLA-style logic blocks were originally deployed in the early PLDs. Due to recent research developments in the FPGA community, PLA-style logic blocks are becoming an effective storage alternative in modern FPGAs. We propose an integrated approach with structural clustering and functional decomposition to implement the circuit using the minimum number of PLA-style logic blocks. The structural clustering method is based on the concepts of Maximum Fanout Free Cone and Maximum Fanout Free Subgraph. In order to effectively use PLA-style logic blocks in large clusters, single-output and multiple-output functional decompositions are used to decompose large clusters so that the encoding functions and base functions can be mapped into PLA-blocks. Furthermore, implicit representation of the crucial steps in the functional decomposition is used to consider (1) number of inputs; (2) number of product terms; (3) number of outputs required for the PLA-block synthesis. Our approach also considers multiple PLA-blocks for individual large cluster so that better area reduction can be obtained. We have developed an algorithm called PLA Syn that can be used in the logic synthesis flow for CPLDs and FPGAs with PLA-blocks. MCNC benchmarks are used to test PLA Syn and the experimental results are compared with TEMPLA. PLA Syn shows 10.24% improvements over TEMPLA, in terms of the number of PLA-blocks needed to implement the circuit.