Defect reduction methodology for advanced copper dual damascene oxide etch

In the semiconductor industry, end of line process and tool requirements are becoming increasingly stringent. The tight geometries found in small feature sizes contribute to the faster chips the market demands, but also require improved performance with respect to defect density. Acceptable defect densities from just a few years ago are now becoming the killer defects of today. Dual damascene processes demand cleanliness since defects at trough etch result in opens, but could also cause problems with later via etch process steps. IBM's Vermont facility recently completed a successful defect reduction program on a Lam 4520XLE oxide etch system used for copper dual damascene. Defects were identified using inline metrology. The defect reduction program successfully identified marginal components, corrected these components, then tracked the defect improvements through both inline metrology and yield controls. At the successful completion of the project, a Mean Time Between Clean increase up to 7.5/spl times/ has been demonstrated with no degradation of line performance. This paper will discuss the methodology used in determining the source of the defects, correcting marginal hardware, verifying the defect improvement, and using monitor wafers to help separate the tools in question from the rest of the manufacturing line. A statistical approach will be discussed that helped to reduce the variability of the line controls. This approach ultimately allowed the increase in MTBC while keeping yields constant.