SmartBit/sup TM/: bitmap to defect correlation software for yield improvement

The need of higher yields on the wafer-manufacturing environment is pushing the yield analysts to develop new techniques and tools for yield improvement. With this scope, we present SmartBit/sup TM/, a software tool that provides detailed information about yield limiters by correlating bitmap to in-line defect data in an automatic mode, expediting the yield learning task. Based on the spatial correlation of bitmap data and the information of defects coming from the in-line inspections, SmartBit/sup TM/ provides a pareto where yield loss sources are separated and weighted by impact. SmartBit/sup TM/ also offers detailed information about the killer defects (defect class, origin, size, kill ratio and more) into a set of reports specially designed to obtain an overall view about the main problems affecting the fab yield. This is the key to fast and efficient yield learning. These reports are generated automatically using data from the full production of memory-products enhancing the reliability and completeness of the analysis.