Hardware implementation of fast neural networks using CPLD

We present a method to implement trained neural networks on digital programmable hardware. The neural network is trained off-line using a microprocessor system and suitable software. Thereafter the trained neural network is transferred to the hardware implementation. In order to reduce the costs, the network nodes are implemented as multiplexed structures requiring a certain number of clocks for the execution of each iteration. However, in order to increase the overall processing speed the pipelining structure can be also used. It only delays the response with a few microseconds, depending on the clock rate and network complexity. The hardware implementation of neural network using programmable logic devices allows boosting the processing speed, compared to the software implementation, to alternatively reduce the overall costs and provide similar flexibility as the software approach.