Gate Leakage Suppression and Breakdown Voltage Enhancement in p-GaN HEMTs Using Metal/Graphene Gates

In this article, single-layer intrinsic and fluorinated graphene were investigated as gate insertion layers in normally-OFF p-gallium nitride (GaN) gate high electron mobility transistors (HEMTs), which wraps around the bottom of the gate forming Ti/graphene/p-GaN at the bottom and Ti/graphene/SiNx on the two sides. Compared to the Au/Ti/p-GaN HEMTs without graphene, the insertion of graphene can increase the I
_ON
/I
_OFF
ratios by a factor of 50, increase the V
_TH
by 0.30 V and reduce the OFF-state gate leakage by 50 times. Additionally, this novel gate structure has better thermal stability. After thermal annealing at 350 °C, gate breakdown voltage (BV) holds at 12.1 V. This is considered to be a result of the 0.24 eV increase in Schottky barrier height and the better quality of the Ti/graphene/p-GaN and Ti/graphene/SiNx interfaces. This approach is very effective in improving the I
_ON
/I
_OFF
ratio and gate BV of normally-OFF GaN HEMTs.