Analysis and implementation of interface for heterogeneous system

We designed asynchronous event logic library with 0.25 /spl mu/m CMOS technology and high-speed asynchronous FIFO operating at 1.6 GHz. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for freeing of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, we implemented high-speed 32 bit-interface chip for heterogeneous system. The size of the core is about 1.1 mm/spl times/1.1 mm.