Yield Analysis for Electrical Circuit Designs: Many Problems and Some Recent Developments in Electronic Engineering

A high production yield, Y = 1 - p_fail, and thus a low failure rate, p_fail, is a key requirement for successful chip design and the design of many other technical products and systems. We focus on IC design in the analog and mixedsignal domains, where Monte Carlo (MC) techniques have been a standard method for many years (see "Important Monte Carlo Rules Engineers Should Know"). Circuits have to be reliable under certain ranges of environmental parameters, such as supply voltage (V) and temperature (T). Furthermore, the set of semiconductor technology parameters (P) varies significantly, from die to die (global variations) to device to device (local variations, called mismatch). Many circuit tricks are known to minimize all of these influences (for example, using cascodes for a high power-supply rejection, differential pairs to cancel out threshold voltages, special layout techniques, and so on), but at some point problems become hard to anticipate, and further improvements are difficult to achieve. We must accept such variations and need to analyze their impact on production yield, which is a function of these parameters and the specifications (such as design topology and component sizes, among others).