Multi-line crosstalk and common-mode noise analysis

The rapid increase in integration level and GHz clock rates are placing increasing demands on the on-chip interconnections for large chips that now contain a substantial portion of the total system. In this environment, noise containment is becoming increasingly difficult. Experimental verification is presented of a multi-line synthesis approach for crosstalk and common-mode noise evaluation. The need for proper accounting of the frequency-dependent current distribution through the finite impedance of the reference conductors is highlighted with examples of wide data-bus structures.