Fast modeling of core switching noise on distributed LRC power grid in ULSI circuits

A sophisticated on-chip power grid model consisting of distributed LRC elements is proposed for on-chip power distribution analysis. Fast equations for peak noise estimations are formulated. Noise distribution on a power grid with any topology is efficiently and accurately computed. HSPICE simulations confirmed its efficiency and accuracy. The model is suitable for both early stage analysis and post-layout verifications in on-chip power distribution design. Global and local optimization such as buffer sizing, power bus sizing, and on-chip decoupling capacitor placement can be easily conducted.