Tradeoffs in modeling the response of power delivery systems of high-performance microprocessors

This paper discusses some tradeoffs associated with building a partial element equivalent circuit (PEEC)-based distributed circuit model for the power delivery systems of high-speed microprocessors packaged in a ceramic pin grid array (CPGA) form factor. The main focus of the paper is on how specific simplification of the model geometry affects the accuracy of the results. Moreover, the tradeoffs between speed and accuracy associated with the additional approximations to the numerical methods used to extract the equivalent circuit parameters are also discussed. Finally, numerical results for the microprocessor disturbances on the power system of typical CPGA packages are presented.