The SIMD architecture for the post-stage tasks of motion estimation

A new architecture using only a single module to implement the post stage tasks of motion estimation is proposed, which has a single instruction stream over multiple data streams (SIMD). Under the control of a simple RISC-like core, an improved tree array concurrently executes vector instructions. A block memory scheme and an evenly time sharing accessing method simplify the management of the on chip data memory and also reduce the memory capacity. A circuit based on this architecture has been integrated by NEL Corporation (NTT Electronics, Japan) into the single MPEG-2 MP@ML encoder chip using 0.25 /spl mu/m CMOS technology.