Structural test in a board self test environment

In this paper, a novel technique for the verification of board level connections on PCBs is presented. The time domain method is used to identify whether a pin connection is faulty or not. The test pulse and evaluation circuitry are part of the chip. Although the chip size increases slightly, the method is highly efficient. No ATE is necessary to carry out the test and since only the physical behaviour of the connection from the internal driver via pin to board is examined, no test vectors are needed. The test time and the test preparation time are lower compared with conventional test methods.