Defect screening challenges in the Gigahertz/Nanometer age: keeping up with the tails of defect behaviors

Today's semiconductor manufacturers are moving to more DFT and structurally based testing to reduce capital and engineering investments for test. A number of test methodologies essential for delivering acceptable product quality face new challenges as the industry moves to new process technologies below 200 nm and devices in the GHz range as designs depart from "pure CMOS" with new types of circuits to deliver more performance and lower power. VLSI logic performance has become limited more by interconnect and parasitic reactance than transistor performance and will be more so as devices that push the limits of noise and supply scaling towards 1.O V. The "tails" of defect-device interactions will increasingly include more failures that are sensitive to speed, temperature and voltage, i.e., test coverage completeness is less likely to occur with only stuck at based testing. The industrial test challenge is to keep up with these "tails": to understand how they are reshaped by ongoing changes in circuits and process technologies and to reshape old and add new DFT and test methodologies to enable acceptable product quality at acceptable cost moving forward. Actual examples of "tails" of defect coverage learnings and tradeoffs will be presented as part of this special session at the conference.