Optimal analog trim techniques for improving the linearity of pipeline ADCs

This paper investigates the issue of capacitor trimming to improve the linearity of pipeline ADCs that use switched capacitor sub-DACs. Capacitor mismatches create linearity errors, which deteriorate THD, SINAD and SFDR performance of the ADC in communication applications. Measurement of capacitor mismatches and generation of trim capacitor values are discussed. The derivations are for 2-bit-per-stage pipeline ADC architectures and they can easily be extended for any pipelined ADC. Finally, the effectiveness of the overall capacitor trimming process in terms of cost and performance is analyzed for a 12 bit 40 MSPS ADC.