VLSI implementations of fuzzy logic controllers for rate-adaptive pacemakers

An efficient fuzzy logic-based control algorithm for rate-adaptive cardiac pacemakers has been developed recently. This algorithm offers good adaptation of the pacing rate to the physiological needs of the patient and easy personalization. However, its usefulness depends on the details of practical implementation such as the necessary hardware resources, programmability, accuracy and power consumption. This work presents a study of several possible implementations including ASIC chips designed specifically for this application as used as implementations in commercially available microprocessors.