A high-performance body-charge-modulated SOI sense amplifier

Dynamic CMOS SOI sensing circuits are prone to performance variation and mismatch in transfer characteristics (Kuang et al, 1997; Allen et al, 1999) as a result of hysteretic body potential and V/sub t/ differences. In dual-railed RAM and register file applications, repetitive polarized read operations performed by a sense amplifier can cause significant asymmetric charge accumulation, body voltage bias, sense point runaway, and consequent functional failures. Tracking of threshold voltages requires tight control of critical device body voltages in addition to matching of other layout and electrical parameters commonly deemed essential for analog designs. This paper presents a dynamic body charge modulation technique to address the history-induced mismatch in latch-type sense amplifiers while attaining high performance for every access cycle. The same method can also be applied to other cross-coupled differential circuit topologies where mismatch can not be tolerated. By symmetrically charging the FET bodies that are connected through two "flooding" FETs to a voltage rail, matching device characteristics can be achieved or restored each time the sense amplifier is activated. This charge flooding mechanism, as opposed to emptying the body of charges (Kuang et al, 1999), retains true and predictable low-V/sub t/ operation. By consistently elevating the sensing FET bodies to the same potential, we always start a high-performance read cycle with bodies well disposed.