An impact of GIDL off leakage on low-power sub-0.2 /spl mu/m SOI CMOS applications

The speed advantage of SOI CMOSFETs has exclusively been claimed for front-end applications (Ajmera et al, 1999), but its potential for low-power applications has rarely been discussed. Recently, it was reported that BF (body floating)-enhanced short-channel effects increase V/sub t/-limited off leakage, for which V/sub t/ must be larger than bulk CMOS, thus resulting in no performance merit in the sub-0.2 /spl mu/m class (Chau et al, 1997). In this paper, we analyze the off leakage current I/sub off/ and aim to suppress I/sub off/ to the bulk level for low-power applications (I/sub off/ level /spl sim/10/sup -11/ A//spl mu/m). In such a low I/sub off/ regime, sub-0.2 /spl mu/m SOI has been found to suffer from another I/sub off/ component, i.e. GIDL (gate-induced drain leakage), especially for nMOSFETs. We show that lowering V/sub dd/ is very effective to reduce GIDL to a comparable level with bulk CMOS while still retaining a speed advantage and dynamic-power reduction.