SLOTFET fabrication of self-aligned sub-100-nm fully-depleted SOI CMOS

In recent years, substantial efforts have been directed toward development of SOI CMOS circuits, with gate lengths scaled to the sub-100 nm regime. These efforts have been motivated by the potential of low voltage, low power, and high speed performance of SOI CMOS in comparison to bulk devices (Hu, 1998). In this work, we describe a new sub-100 nm CMOS SLOTFET fabrication process using conventional 0.25 /spl mu/m SOI CMOS processing techniques with DUV 248 nm photolithography, and we present experimentally measured p- and n-MOSFET characteristics. In comparison to an existing fully-depleted 0.25 /spl mu/m SOI CMOS process (Liu et al, 1998), the SLOTFET process offers several important advantages, including (i) self aligned T-gate, allowing lower gate resistance required for high-f/sub max/ RF transistors, (ii) island spacers, suppressing parasitic sidewall transistors, (iii) recessed SOI channel region, minimizing short-channel effects and drain-induced-barrier lowering (DIBL), and (iv) raised source-drain region, allowing the maximum advantage of a cobalt salicide process for low source-drain series resistance. In the first SLOTFET fabrication run, both p- and n-MOS devices exhibited very promising sub-threshold slopes, drive current, off-state leakage, and DIBL; fine tuning is needed to optimize drive current, threshold voltage, and series resistance.