SOI at IBM: current status of technology, modeling, design, and the outlook for the 0.1 /spl mu/m generation

This paper reviews the evolution of partially depleted (PD) CMOS SOI technology at IBM. Several aspects of this development leading to successful fabrication of high-performance microprocessors are discussed. They include SOI-specific device design and process modifications; creation of compact device models for circuit simulation (SPICE-like models); and development of circuit styles and strategies employed in the design of CMOS VLSI on PD SOI. Since these strategies address issues and problems that arise on PD SOI circuits such as delay hysteresis, and noise margin reduction, they are discussed in detail. The discussion is focused on the 0.18 /spl mu/m and 0.13 /spl mu/m generations, with some deliberations on the 0.10 /spl mu/m node.