Delay analysis of an input buffered ATM switch under two different scheduling disciplines

Depending on the buffer arrangement, space division ATM switch architectures are classified into three main categories: input buffered, output buffered and centrally buffered switches. Among them, input buffered ATM switch is the most simple, cheap and popular switch architecture but it exhibits limited throughput performance due to head of line blocking (HOL) conflict. This problem occurs because of the contention in the unscheduled arrival of ATM cells to the switch. A lot of effort has been expended in attempting to resolve this conflict but it is found that this HOL blocking still induces variable delays in ATM cells while transmitting them from input ports to output ports. This paper analyzes the delay distribution of these cell's waiting times that they may have to experience while being in the buffers at the inputs of the switch before transmission. So far researchers have concentrated only on the average and mean values of the cell's delays but the analysis of the delay distribution of cells gives complete information of switch behaviour and performance under different conditions such as different switch sizes, switch loadings etc. For this purpose we have developed a simulation model under two different cell-scheduling policies (random and polling). To obtain the interested study parameters such as probability mass function and cumulative distribution function of each cell's delay, we have simulated the model for different switch sizes and input loads. It can be revealed from the comparison results that the switch exhibits better performance under the random selection policy as compared to the polling selection technique.