Reliability Concerns on LDMOS With Different Split-STI Layout Patterns

Compared with the full shallow trench isolation (full-STI) lateral double-diffused MOS (LDMOS), the split-STI LDMOS has been demonstrated as a superior device with better breakdown voltage (BV
_OFF
and specific on-resistance (
${R}_{ {\scriptstyle\mathrm{ON}},\text {sp}})$
by virtue of its low resistance current path and dielectric reduced surface field effect. The layout of STI may not only be restricted in one pattern. Instead, it can have a variety of changes based on the split-STI structure. Actually, improvement of
${R}_{ {\scriptstyle\mathrm{ON}},\text {sp}}$
can be achieved upon modifying the STI layout pattern. In this way, four STI layout patterns, named split-STI, stair-STI, slope-STI, and H-shape-STI, are proposed. However, there is lack of information about the impacts of STI layout patterns on the reliability features of LDMOS. Therefore, in this article, the reliability features of the LDMOS with different STI layout patterns are investigated in detail, including electrical safe operating area (e-SOA), electro-static discharge (ESD) robustness, and hot carrier injection (HCI) degradation. Combining the experiment and technology computer-aided design (TCAD) simulation, the root causes of different reliability features are analyzed and discussed. Comparing them each, the LDMOS with H-shape-STI is recommended because of its better reliability features.