Design Impacts of Back-End-of-Line Line Edge Roughness

One of the main issues of EUV lithography is Line Edge Roughness (LER) on photo-resists, which significantly impacts yield at sub-30 nm pitches. In this work, an analytical model of LER is presented and analyzed for yield loss induced by open/short failures, cut mask defects, enhanced time dependent dielectrics breakdown (TDDB) failures for metal wires with different geometries, electro-migration (EM) impacts from the presence of LER on SRAM bitlines, and finally, LER impacts on functional errors. The model will be evaluated on single and double patterned designs with metal pitches of 24 and 28 nanometers. We show experimental results and give specific criteria in which LER thresholds can be relaxed without negatively impacting yield and path delay. This is a critical issue as higher LER tolerance allows exponential increase in throughput and thus reduces cost of fabrication.