Dynamic Voltage Overshoot During Triggering of an SCR-Type ESD Protection

During triggering of an on-board ESD protection, e.g., an SCR, its voltage may temporarily rise to a large value. This work identifies and distinguishes the two major factors that contribute to this voltage overshoot: (1) the conductivity modulation in the silicon and (2) the inductance of the metal traces. The overshoot is shown to have a major impact on the residual current into the IC during a system level discharge (ESD gun test), in particular in high-speed interfaces, such as USB3. This work presents a physics-based behavioral model which accurately describes both contributions to the voltage overshoot. The conductivity modulation model is based on the premise that the doping concentration of a region in the SCR is insufficient to conduct the trigger current. It follows that a minimum charge must be injected into the low-doped region to enable conduction of the trigger current. SCR triggering is delayed until this minimum charge has been injected. During the delay time, the SCR voltage is determined by the high (~1 kg) off-resistance of the device. After triggering, the voltage is determined by the low-impedance (~0.25 Ω) on-resistance. The net effect is a voltage overshoot. This first overshoot is followed by a second inductive voltage overshoot at the time when L.dI/dt is maximum. The paper demonstrates how the resulting model can be used to improve system level robustness for a typical USB3 interface.