Best of both worlds in parallel digital adders

In this paper, a new approach to the carry-bits calculation is proposed, parallel within the limits of component ideality. Such an approach shows that, from a logical point of view, the parallel carry-bits calculation is no more complex than the sequential calculation. An example of implementation in TTL is given and a SPICE simulation is carried out. The solution is compared to a traditional one, to estimate the effectiveness of the new approach. The obtained adder results are simple, like the results obtained with sequential carry, and are fast, like the results obtained with parallel carry.