Branch prediction in multi-threaded processors

There has been a growing interest in the use of multithreading to speed up the execution of a single program. This paper highlights the problems involved in performing accurate branch predictions in single-program multi-threaded (SPMT) processors, where branches are predicted out of program order, and microarchitectural aspects affect branch history. In particular, it shows that the recorded branch history could become insufficient, discontinuous, outdated, scrambled, or inaccurate, depending on the specifics of the microarchitecture. Measurements obtained with a multiscalar simulator show that the affects on the recorded branch history cause the branch misprediction ratios to increase from an average of 6.5% to an average of 41.0% for global branch history-based schemes such as gshare, and from an average of 6.7% to an average of 11.5% for per-address history-based schemes such as Fag. The paper also investigates techniques for overcoming the adverse effects of the microarchitecture's impact on branch history. These techniques rely on extrapolation of outdated history so as to make it up-to-date, and correlation with thread-level information so as to partition scrambled history into a set of unscrambled history parts. Experimental evaluation of the proposed techniques on a multiscalar simulator indicates that these techniques, especially a hybrid of extrapolation and correlation, can substantially lower the branch misprediction ratios.