Path delay fault testability analysis

The paper deals with the problem of testing delay path faults. We present results obtained with a newly developed test pattern generator. This generator is based on the use of reduced ordered binary decision diagrams (ROBDDs) and reveals many advantages as compared with other ATPGs published in the literature. An important contribution of the paper is the analysis of various testability features of digital circuits in respect to path delay faults. It was applied to the ISCAS89 benchmark and other circuits. The proposed testability measures are helpful in codesigning deterministic and pseudorandom delay tests as well as in improving circuit testability.