Implementation of a multiprocessor system with distributed embedded DRAM on a large area integrated circuit

An architecture of a multiprocessor coding system suitable for large area integration has been developed. Application field is video coding according to the international standards ISO MPEG-2 and ITU-T H.263 or similar methods. It is based on processor nodes, which consist of a 1.9 GOPS video signal processor AxPe, 4 MBit of embedded DRAM, and digital video interfaces for data input and output as well as for inter-processor communication. Four of these processor nodes can be fabricated with a single mask set on a 0.25 /spl mu/m CMOS circuit of 2/spl times/2 cm/sup 2/, which is called AxPe subsystem. By overlapping manufacturing and cutting out of 2/spl times/2 of AxPe subsystems afterwards, a large area integrated circuit (LAIC) with 16 processor nodes can be realized. The upper metal layers of each AxPe subsystem contains connection structures at the chip boundaries for this purpose. Redundancy techniques ensure the functionality of the LAIC even in the case of defect processor nodes.