Mechanical stress related instabilities in silicon under metal coverage

Mechanical stress related instabilities in silicon bulk material under integrated circuit (IC) metallization are investigated. The test structures based on Wheatstone bridge configuration in which two out of four resistors were covered by wide aluminium stripes were fabricated especially for this purpose. Calculations based on the piezoresistance effect were utilized to estimate the mechanical stress in the silicon substrate. Also, finite element modeling (FEM) of the fabricated test structures has been performed. Both results, experimental and numerical, show that metallization involves an additional stress term. In the silicon buffer, The piezoresistance can influence the matching characteristics of ICs and also produce a time-drift of IC performance due to the time-drift of mechanical stress. Resistance mismatching of more than 1000 ppm was measured when the resistors were covered by aluminum. A covered resistance drift of 245 ppm due to aluminum plastic deformation was measured when heating tests mere applied. Finally, the simulation results for the prediction of the stress levels in silicon covered with metal lines of various widths are presented. For a 4 /spl mu/m-width aluminum line it was recognized a safe distance of 10 /spl mu/m.