Low power multi-module, multi-port memory design for embedded systems

In this paper we describe a multi-module, multi-port memory design procedure that satisfies area and/or energy constraints. Our procedure consists of use of ILP models and heuristic-based algorithms to determine (a) the memory configuration with minimum area, given the energy bound, (b) the memory configuration with minimum energy, given the area bound, (c) array allocation such that the energy consumption is minimum for a given memory configuration (number of modules, size and number of ports per module). The results obtained by the heuristics match very well with those obtained by the ILP methods.