A high-speed MAP architecture with optimized memory size and power consumption

This paper presents a novel high-speed maximum a posteriori (MAP) decoder architecture with optimized memory size and power consumption. Area and power consumption are both reduced significantly, compared to the state-of-the-art. The architecture is also capable of decoding recursive systematic convolutional codes which are the constituent codes of the revolutionary turbo-codes and related concatenation schemes. The architecture is highly scalable with respect to throughput, expanding its applicability over a wide range of throughput requirements (300 Mbit/s-45 Gbit/s and above).