A 3D DCT architecture for compression of integral 3D images

A VLSI architecture for the three-dimensional discrete cosine transform (3D DCT) is proposed. The 3D DCT is decomposed into 1D DCTs computed in each of the three dimensions. The focus of this paper is in the design of the matrix transpose required prior to the computation of the final 1D DCT which corresponds to the third dimension. This matrix transpose is divided into N memory units each performing the row-column transpose and switching networks to allow correct read and write. This architecture uses 3N multiplier-accumulators and N+1 (N/spl times/N)-words memory transpose to evaluate an (N/spl times/N/spl times/N)-point DCT at a rate of one complete 3D transform per N/sup 3/ clock cycles, where N is even.