A low power VLSI prototype for low bit rate video applications

This paper presents a low power architecture for video application. The architecture is divided into two parts: motion estimation and motion compensation. In the motion estimation part, the modified three step search (TSS) algorithm is used to reduce the computational cost and the memory access. Also, the mesh is coded as a tree and a sequence of motion vectors to ensure low bit rate. In the motion compensation part, using a modified affine transform that reduces the complexity of the motion compensation reduces the computational cost. The performance of this architecture is also presented.