77% power added efficiency surface-mounted bipolar power transistors for low-voltage wireless applications

To increase the power added efficiency (PAE) and gain (G/sub p/) of low-voltage RF bipolar power transistors for cellular applications, we present a novel wafer-scale packaging concept based on our silicon-on-anything technology allowing for a strong reduction of device and packaging parasitics. Using this concept, we have achieved a record PAE of 77% and G/sub p/ of 14 dB at 0.5 W, 1.8 GHz and 3.5 V supply voltage for an assembled device approaching the theoretical class-AB limit of 78.5%. We also present a 15 V double epi-layer integrated cascode with a gain of 24 dB at 1.8 GHz.