Analysis and compact modeling of a vertical grounded-base NPN bipolar transistor used as an ESD protection in a smart power technology

A thorough analysis of the physical mechanisms involved in a vertical grounded-base NPN bipolar transistor (VGBNPN) under ESD stress is first carried out by 2D-device simulation, square pulse measurements (TLP) and photoemission experiments. As a result, we propose a compact model using a new physics-based avalanche formulation. This allows reproduction of the unexpected low value of the VGBNPN snapback holding voltage under TLP stress.