Vertical and planar merged MOS transistors for low-voltage high-speed ULSI

Novel vertical and planar merged MOS (VMMOS and PMMOS) structures which increase the packaging density for advanced high-speed low-voltage low-power ULSI are examined. The VMMOS and PMMOS, where electrons and holes move along common channels, are simulated using 2D-numerical device-circuit simulators (DCS). Various VMMOS and PMMOS-SOI constructions providing integration density of up to 10/sup 9/ elements/cm/sup 2/ (0.1 /spl mu/m design rule) at supply voltages of 0.2-0.8 V have been simulated and optimized.