Implementation of a real-time, frequency selective, RF channel simulator using a hybrid DSP-FPGA architecture

A low cost, frequency selective, RF channel simulator architecture is explored. The system is implemented almost entirely in the digital domain by use of IF sampling with the signal processing performed in a high-end floating point DSP and an FPGA. The prototype system costs less than $3900 and is capable of simulating three delay taps. It is believed that a system capable of simulating 12 delay taps with a bandwidth of 5 MHz could be built at a cost less than $2000, at least an order of magnitude cheaper than commercially available channel simulators of comparable performance.