A 660-/spl mu/W 50-Mops 1-V DSP for a hearing aid chip set

This article presents the flow and techniques used to design a low-power digital signal processor chip used in a hearing aid system implementing multiband compression in 20 bands, pattern recognition, adaptive filtering, and finescale noise cancellation. The pad limited 20 mm/sup 2/ chip contains 1.3 M transistors and operates at 2.5 MHz under 1.05-V supply voltage. Under these conditions, the DSP consumes 660 /spl mu/W and performs 50 million 22-bit operations per second, therefore achieving 0.013 mW/Mops (milli-watts per million operations), which is a factor of seven better than prior results achieved in this field. The chip has been manufactured using a 0.25-/spl mu/m 5-metal 1-poly process with normal threshold voltages. This low-power application-specific integrated circuit (ASIC) relies on an automated algorithm to silicon flow, low-voltage operation, massive clock gating, LP/LV libraries, and low-power-oriented architectural choices.