High throughput FIR filter design for low power SoC applications

This paper introduces a framework for the implementation of high throughput FIR filters for low power applications. The design methodology incorporated in this framework results in highly flexible FIR filter cores, which are open to exploitation by coefficient and data manipulation techniques resulting in significant power savings. Power savings are achieved within the multiplier units and on system buses making the resulting FIR filters ideal for use as IPs on SoC based platforms. The paper describes the design methodology, evaluation environment and presents results with a number of FIR filter example benchmarks under different design constraints.