Formal representation of gated clock designs

The action systems formal framework has recently been applied to the area of asynchronous and synchronous VLSI design. In this paper, we present aspects of formal gated clock design. This proves useful when targeting mixed-architecture designs: devices composed of subsystems that operate in an asynchronous manner with respect to each other, even though some of them may have synchronous implementations. The modeling of gated clock systems is built on top of the synchronous operators.