An effective modeling technique for the delay calculation and the skew analysis of clock grid designs

We propose an effective modeling technique for a clock grid. This technique enables the delay calculation and the skew analysis of a large multiple-driven clock grid with speed improvements and no loss of accuracy while previously published algorithms cannot. Speed improvements are achieved by efficient calculation of "effective capacitance" and replacing many drivers of the clock grid with an equivalent driver model. The experimental results show that this modeling technique is two orders of magnitude faster than the iterative method using the superposition principle and several orders of magnitude faster than Hspice within 5% errors.