Design self-synchronized clock distribution networks in an SoC ASIC using DLL with remote clock feedback

This paper presents an automatic clock skew control scheme in an SoC ASIC that inserts appropriated delays on the outputs of the clock generator such that the target module clocks MCK-1 through MCK-n are all in phase (or 1800 out of phase) with PLL's input system clock. The clock distribution network consists of multiple delay circuits with the remote feedback clock inputs, which insert different amount delays to the output clocks that drive each of the modules in the SoC. Using the remote feedback clock input, the internal DLL circuit aligns the phase of the module clocks with the PLL clock such that they are either in phase or 180/spl deg/ out of phase with respect to each other, as defined by the equation: clock-buffer-delay+RC delay=n/2* clock period. Thus, this scheme guarantees that all clocks in various modules are in phase with the PLL clock.