Digit-serial fixed coefficient complex number multiplier-accumulator on FPGAs

In this paper we consider the design of a digit-serial multiplier for the implementation of a complex number multiplier-accumulator (CMAC) on FPGAs. In this case, fixed coefficient multipliers and pipelined at LUT-level structures have been considered. Partial products generators based on look-up tables and multibit Booth recoding are used to reduce the area and increase the performance of the circuit. The efficient mapping of the 5 bit Booth recoding to generate the partial products is presented as the optimum multibit recoding when Xilinx FPGA devices are used.