High-level synthesis and behavioral VHDL writing style towards a methodology for behavioral IP reuse

The recent emergence of commercial high-level synthesis tools raises the question of specifying IPs at the algorithmic, or behavioral, level. While flexibility of currently used soft IPs is limited to optimizing the logic synthesis flow, HLS introduces architectural flexibility and allows a closer adaptation to the requirements of a target application. Since reusing behavioral code may be hazardous due to the high abstraction level of the specification, a methodology should be defined in order to provide a framework for ensuring synthesizability of a behavioral IP, performance predictability and tool-independence of the specification. Formalizing the syntax, behavioral semantics and architectural models of commercial HLS tools is the first step for defining such a methodology. In this paper, we introduce the first results of an experiment consisting of analyzing the architectural model of a commercial HLS tool.