Pin Accessibility Prediction and Optimization with Deep Learning-based Pin Pattern Recognition

Since the process node of semiconductor keeps scaling down, standard cells become much smaller and cell counts are dramatically increased. Standard cells on the lower metal layers severely suffer from low routability due to high pin density, low pin accessibility, and limited routing resources. Fig. 1 gives an example of the bad pin accessibility of cell C2 affected by the adjacent cell C1. It can be observed that the access points of pin B are blocked by the metal 2 (M2) routing segments routed from Pin A and Pin C, so an M2 short design rule violation (DRV) will be induced when dropping a via12 on Pin B. This example shows that pin accessibility is not only determined by cell layout design but also strongly affected by adjacent cells.