A low-power design technique for digital signal processing applications

We present a novel design technique to reduce the power consumption of the data paths. Our technique is based on the observation that a circuit can be optimally synthesized for a particular type of inputs. We use logic-level techniques to re-synthesize data path elements to be effective in terms of power dissipation. The regularity of data path elements are destroyed, however, voltage scaling can be applied, which result in power savings.